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19-1835; Rev 0; 10/00
KIT ATION EVALU E AILABL AV
Small, Dual, High-Efficiency Buck Controller for Notebooks
General Description Features
o Free-Running On-Demand PWM o Selectable Light-Load Pulse-Skipping Operation o 1% Total DC Error in Forced-PWM Mode o 5V to 20V Input Range o Flexible Output Voltages OUT1: Dual ModeTM Fixed 2.5V or 1V to 5.5V Adjustable OUT2: Dual Mode Fixed 1.8V or 1V to 5.5V Adjustable o Output Undervoltage Protection o Complementary Synchronous Buck o No Current-Sense Resistor o 4.65V at 25mA Linear Regulator Output o 4A V+ Shutdown Supply Current o 5A VL Shutdown Supply Current o 950A Quiescent Supply Current o Tiny 16-Pin QSOP Package
MAX1761
The MAX1761 dual pulse-width-modulation (PWM), step-down controller provides high efficiency, excellent transient response, and high DC output accuracy in an extremely compact circuit topology. These features are essential for stepping down high-voltage batteries to generate low-voltage CPU core, I/O, and chipset RAM supplies in PC board area critical applications, such as notebook computers and smart phones. Maxim's proprietary Quick-PWMTM quick-response, constant-on-time PWM control scheme handles wide input/output voltage ratios with ease and provides "instant-on" response to load transients while maintaining a relatively constant switching frequency. The MAX1761 achieves high efficiency at reduced cost by eliminating the current-sense resistor found in traditional current-mode PWMs. Efficiency is further enhanced by its ability to drive large synchronous-rectifier MOSFETs. The MAX1761 employs a complementary MOSFET output stage, which reduces component count by eliminating external bootstrap capacitors and diodes. Single-stage buck conversion allows this device to directly step down high-voltage batteries for the highest possible efficiency. Alternatively, two-stage conversion (stepping down the +5V system supply instead of the battery) at a higher switching frequency allows the minimum possible physical size. The MAX1761 is intended for CPU core, chipset, DRAM, or other low-voltage supplies. The MAX1761 is available in a 16-pin QSOP package. For applications requiring greater output power, refer to the MAX1715 data sheet. For a single-output version, refer to the MAX1762/MAX1791 data sheet.
Ordering Information
PART MAX1761EEE TEMP. RANGE -40C to +85C PIN-PACKAGE 16 QSOP
________________________Applications
Notebooks and PDAs Digital Cameras Handy-Terminals Smart Phones 1.8V/2.5V Logic and I/O Supplies
TOP VIEW
FB1 1 OUT1 2 REF 3 ON2 4 V+ 5 ON1 6 OUT2 7
Pin Configuration
16 DH1 15 CS1 14 DL1
MAX1761
13 VL 12 GND 11 DL2 10 CS2 9 DH2
Quick-PWM and Dual Mode are trademarks of Maxim Integrated Products.
FB2 8
QSOP 1
________________________________________________________________ Maxim Integrated Products
For price, delivery, and to place orders, please contact Maxim Distribution at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Small, Dual, High-Efficiency Buck Controller for Notebooks MAX1761
ABSOLUTE MAXIMUM RATINGS
V+ to GND ..............................................................-0.3V to +22V VL to GND ................................................................-0.3V to +6V VL to V+ .............................................................................+0.3V OUT_, ON2 to GND ..................................................-0.3V to +6V ON1, DH_ to GND ........................................-0.3V to (V+ + 0.3V) FB_, REF, DL_ to GND.................................-0.3V to (VL + 0.3V) CS_ to GND .....................................................-2V to (V+ + 0.3V) REF Short Circuit to GND ...........................................Continuous Continuous Power Dissipation 16-Pin QSOP (derate 8.3mW/C above +70C) ..........667mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature.........................................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, V+ = 15V, CVL = 4.7F, CREF = 0.1F, VL not externally driven unless otherwise noted, TA = 0C to +85C, unless otherwise noted.) (Note 1)
PARAMETER PWM CONTROLLERS Input Voltage Range DC Output Voltage Accuracy (Note 3) Output Voltage Adjust Range OUT_ Input Resistance FB_ Input Bias Current CS_ Input Bias Current Soft-Start Ramp Time On-Time (Note 4) Minimum Off-Time (Note 4) BIAS AND REFERENCE IL Quiescent Supply Current I+ IL I+ VL VREF IREF FB1 = FB2 = GND, VL = 5V, VOUT1 and VOUT2 forced above regulation point FB1 = FB2 = GND, VOUT1 and VOUT2 forced above regulation point VL undriven VL = 5V 0.60 0.95 0.38 5 4 4.5 1.98 10 1.6 1.94 4.65 2 1.20 1.70 mA 0.65 10 10 4.75 2.02 8 A A V V mV A V mA tON tOFF VFB_ = 1V, VL = 5V VCS_ = 0, VL = 5V Zero to full ILIM V+ = 10V, VOUT1 = 2.5V, VOUT2 = 1.8V OUT1 OUT2 661 648 V+ VOUT_ (Note 2) V+ = 4.5V to 20V, VL = 4.75V to 5.25V, ON2 = VL FB_ = OUT_ FB1 = GND FB2 = GND 4.5 0.99 2.475 1.782 1 80 -0.1 -1 1700 735 720 400 809 792 500 160 1 2.5 1.8 20 1.01 2.525 1.818 5.5 300 0.1 1 V k A A s ns ns V V SYMBOL CONDITIONS MIN TYP MAX UNITS
Shutdown Supply Current VL Output Voltage Reference Voltage Reference Load Regulation REF Sink Current REF Fault Lockout Voltage
VL = 5V, ON1 = ON2 = GND VL = 0, 5V ILOAD = 0 to 25mA, V+ = 5V to 20V V+ = 5V to 20V, no load IREF = 0 to 50A REF in regulation Falling edge Rising edge
2
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Small, Dual, High-Efficiency Buck Controller for Notebooks
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = 15V, CVL = 4.7F, CREF = 0.1F, VL not externally driven unless otherwise noted, TA = 0C to +85C, unless otherwise noted.) (Note 1)
PARAMETER FAULT PROTECTION Output Undervoltage Threshold (Foldback) Output Undervoltage Blanking Time Current-Limit Threshold Thermal Shutdown Threshold VL Undervoltage Lockout Threshold GATE DRIVERS DH_ Gate Driver On-Resistance (Pullup) DH_ Gate Driver On-Resistance (Pulldown) DL_ Gate Driver On-Resistance (Pullup) DL_ Gate Driver On-Resistance (Pulldown) DH_ Gate Driver Source/Sink Current DL_ Gate Drive Sink Current DL_ Gate Drive Source Current LOGIC CONTROLS ON_ Logic Input High Voltage ON2 Logic Input Float Voltage (Forced-PWM Mode) ON_ Logic Input Low Voltage ON1 Logic Input Current ON2 Logic High Input Current ON2 Logic Low Input Current FB_ Dual Mode Threshold VON2 > 2.0V VON2 < 0.5V, VON1 > 2.0V -1 0 -2 50 1 -1 100 2.0V < VON1 < VL 2.05 1.3 1.7 1.95 0.5 1 3 0 150 V V V A A A mV V+ = 6V to 20V, DH_, high state DH_, low state DL_ , high state DL_, low state VDH_ = 3V, V+ = 6V VDL_ = 2.5V VDL_ = 2.5V 3.7 6.2 3.4 2.0 0.6 0.9 0.5 8 10 8 5 A A A VVL,UVLO VFB,UVFB With respect to the regulation point, no load 60 10 92 -135 100 -120 2.5 160 4.1 4.4
o
MAX1761
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
70
80 32 108 -105
% ms
VFB,UVLO(t) Measured from ON_ signal going high GND - CS_, positive direction GND - CS_, negative direction, ON2 = floating GND - CS_, zero crossing, ON2 = 5V Hysteresis = 10oC Rising edge, hysteresis = 20mV, PWM is disabled below this voltage
mV C
V
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3
Small, Dual, High-Efficiency Buck Controller for Notebooks MAX1761
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, V+ = 15V, CVL = 4.7F, CREF = 0.1F, VL not externally driven unless otherwise noted, TA = -40C to +85C, unless otherwise noted.) (Note 1)
PARAMETER PWM CONTROLLERS Input Voltage Range DC Output Voltage Accuracy (Note 3) Output Voltage Adjust Range OUT_ Input Resistance FB_ Input Bias Current CS_ Input Bias Current Soft-Start Ramp Time On-Time (Note 4) Minimum Off-Time (Note 4) BIAS AND REFERENCE IL Quiescent Supply Current I+ IL I+ VL VREF IREF FB1 = FB2 = GND, VL = 5V, VOUT1 and VOUT2 forced above regulation point FB1 = FB2 = GND, VOUT1 and VOUT2 forced above regulation point VL undriven VL = 5V 1.2 1.7 0.5 10 10 4.5 1.98 10 4.75 2.02 8 A A V V mV A mA tON tOFF VFB_ = 1V, VL = 5V VCS_ = 0, VL = 5V Zero to full ILIM V+ = 10V, VOUT1 = 2.5V, VOUT2 = 1.8V Above regulation point OUT1 OUT2 661 648 809 792 500 V+ VL VOUT_ (Note 2) VL externally driven (Note 2) V+ = 4.5V to 20V, VL = 4.75V to 5.25V, ON2 = VL FB_ = OUT_ FB1 = GND FB2 = GND 4.5 4.75 0.99 2.475 1.782 1 80 -0.1 -1 20 5.25 1.01 2.525 1.818 5.5 300 0.1 1 V k A A s ns ns V V SYMBOL CONDITIONS MIN TYP MAX UNITS
mA
Shutdown Supply Current VL Output Voltage Reference Voltage Reference Load Regulation REF Sink Current FAULT PROTECTION Output Undervoltage Threshold (Foldback) Output Undervoltage Lockout Timer Current-Limit Threshold VL Undervoltage Lockout Threshold
VL = 5V, ON1 = ON2 = GND VL = 0, 5V ILOAD = 0 to 25mA, V+ = 5V to 20V V+ = 5V to 20V, no load IREF = 0 to 50A REF in regulation
VFB,UVFB
With respect to the regulation point, no load
60 10 92 -135 4.1
80 32 108 -105 4.4
% ms mV V
VFB,UVLO(t) Measured from ON_ signal going high GND - CS_, positive direction GND - CS_, negative direction, ON2 = floating VVL,UVLO Rising edge, hysteresis = 20mV, PWM is disabled below this voltage
4
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Small, Dual, High-Efficiency Buck Controller for Notebooks
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = 15V, CVL = 4.7F, CREF = 0.1F, VL not externally driven unless otherwise noted, TA = -40C to +85C, unless otherwise noted.) (Note 1)
PARAMETER GATE DRIVERS DH_ Gate Driver On-Resistance (Pullup) DH_ Gate Driver On-Resistance (Pulldown) DL_ Gate Driver On-Resistance (Pullup) DL_ Gate Driver On-Resistance (Pulldown) DH_ Gate Driver Source/Sink Current DL_ Gate Drive Sink Current DL_ Gate Driver Source Current LOGIC CONTROLS ON_ Logic Input High Voltage ON2 Logic Input Float Voltage (Forced-PWM Mode) ON_ Logic Input Low Voltage ON1 Logic Input Current ON2 Logic High Input Current ON2 Logic Low Input Current FB_ Dual Mode Threshold VON2 > 2.0V VON2 < 0.5V, VON1 > 2.0V -1 0 -2 50 VON1 > 2.0V 2.05 1.3 1.95 0.5 1 3 0 150 V V V A A A mV V+ = 6V to 20V, DH_, high state DH_, low state DL_, high state DL_, low state VDH_ = 3V, V+ = 6V VDL_ = 2.5V VDL_ = 2.5V 8 10 8 5 A A A SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX1761
Note 1: Specifications to -40C are guaranteed by design, not production tested. Note 2: If V+ is less than 5V, V+ must be connected to VL. If VL is connected to V+, V+ must be between 4.5V and 5.5V. Note 3: DC output accuracy specifications refer to the trip-level error of the error amplifier. The output voltage will have a DC regulation higher than the trip level by 50% of the ripple. In PFM mode, the output will rise by approximately 1.5% when transitioning from continuous conduction to no load. Note 4: One-shot times are measured at the DH pin (V+ = 15V, CDH = 400pF, 90% point to 90% point). Actual in-circuit times may be different due to MOSFET switching speeds.This effect can also cause the switching frequency to vary.
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5
Small, Dual, High-Efficiency Buck Controller for Notebooks MAX1761
Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
EFFICIENCY vs. LOAD CURRENT (VOUT = 2.5V, SKIP MODE)
MAX1761 toc01
EFFICIENCY vs. LOAD CURRENT (2.5V, PWM MODE)
MAX1761 toc02
EFFICIENCY vs. LOAD CURRENT (1.8V, SKIP MODE)
90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 V+ = +7V V+ = +12V V+ = +18V V+ = +5V = VL
MAX1761 toc03
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 1 10 100 1000 V+ = +18V V+ = +12V V+ = +7V V+ = +5V = VL
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 V+ = +18V V+ = +7V V+ = +12V V+ = +5V = VL
100
10,000
1
10
100
1000
10,000
1
10
100
1000
10,000
LOAD CURRENT (mA)
LOAD CURRENT (mA)
LOAD CURRENT (mA)
EFFICIENCY vs. LOAD CURRENT (1.8V, PWM MODE)
MAX1761 toc04
EFFICIENCY vs. LOAD CURRENT (3.3V, SKIP MODE)
MAX1761 toc05
EFFICIENCY vs. LOAD CURRENT (3.3V, PWM MODE)
90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 V+ = +12V V+ = +7V V+ = +18V
MAX1761 toc06
100 90 80 70 EFFICIENCY (%) 60 50 40 30 20 10 0 1 10 100 1000 V+ = +12V V+ = +7V V+ = +18V V+ = +5V = VL
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0
V+ = +5V = VL
100 V+ = +5V = VL
V+ = +18V V+ = +12V
V+ = +7V
10,000
1
10
100
1000
10,000
1
10
100
1000
10,000
LOAD CURRENT (mA)
LOAD CURRENT (mA)
LOAD CURRENT (mA)
EFFICIENCY vs. LOAD CURRENT (2.5V, SKIP MODE, 3.5A COMPONENTS)
MAX1761 toc07
FREQUENCY vs. LOAD CURRENT
MAX1761 toc08
VL VOLTAGE vs. OUTPUT CURRENT
-0.05 -0.10 VL ERROR (%) -0.15 -0.20 -0.25 -0.30 -0.35
MAX1761 toc09
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 1 10 100 1000 V+ = +18V V+ = +12V V+ = +7V V+ = +5V
350 300 FREQUENCY (kHz) 250 200 150 100 50 0 SKIP MODE PWN MODE 0 400 800 1200 1600 VOUT = + 1.8V VOUT = + 2.5V VOUT = + 1.8V VOUT = + 2.5V
0
-0.40 -0.45 2000 0
VOUT1 = 2.5V, IOUT1 = 2A, VOUT2 = 1.8V, IOUT2 = 2A 5 10 15 20 25 30 35 VL CURRENT (mA)
10,000
LOAD CURRENT (mA)
LOAD CURRENT (mA)
6
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Small, Dual, High-Efficiency Buck Controller for Notebooks MAX1761
Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. INPUT VOLTAGE (SKIP MODE)
MAX1761 toc10
SUPPLY CURRENT vs. INPUT VOLTAGE (PWM MODE)
MAX1761 toc11
NO-LOAD SUPPLY CURRENT vs. INPUT VOLTAGE (SHUTDOWN)
7 SUPPLY CURRENT (A) 6 5 4 3 2 1 0 ON1 = GND, 0N2 = VL 4.5 6.5 8.5 10.5 12.5 14.5 16.5 18.5 20.5 INPUT VOLTAGE (V)
MAX1761 toc12
0.7 0.6 SUPPLY CURRENT (mA) 0.5 0.4 0.3 0.2 0.1 0 4.5 6.5 ON1 = VL, ON2 = VL NO LOAD
30 25 SUPPLY CURRENT (mA) 20 15 10 5 0 ON1 = VL, ON2 = FLOAT NO LOAD
8
8.5 10.5 12.5 14.5 16.5 18.5 20.5 INPUT VOLTAGE (V)
4.5
6.5
8.5 10.5 12.5 14.5 16.5 18.5 20.5 INPUT VOLTAGE (V)
LOAD-TRANSIENT RESPONSE (2.5A COMPONENTS, VOUT = 2.5V)
MAX1761 toc13
LOAD-TRANSIENT RESPONSE (2.5A COMPONENTS, VOUT = 1.8V)
MAX1761 toc14
OUTPUT OVERLOAD WAVEFORMS (IOUT = 4V, VOUT = 2.5V)
A
MAX1761 toc15
A
A
B
B
B
C 20 s/div A: VOUT, AC-COUPLED, 10mV/div B: INDUCTOR CURRENT, 1A/div C: DL1, 5V/div
C 20 s/div A: VOUT, AC-COUPLED, 5mV/div B: INDUCTOR CURRENT, 1A/div C: DL1, 5V/div
C 100 s/div A: VOUT, 1V/div B: INDUCTOR CURRENT, 2A/div C: DL1, 2V/div
STARTUP AND SHUTDOWN WAVEFORMS (VOUT = 1.8V)
MAX1761 toc16
STARTUP AND SHUTDOWN WAVEFORMS (VOUT = 2.5V)
MAX1761 toc17
A
A
B B
C 500 s/div A: VOUT, 2V/div B: INDUCTOR CURRENT, 2A/div C: DL1, 5V/div
C 500 s/div A: VOUT, 2V/div B: INDUCTOR CURRENT, 2A/div C: DL1, 5V/div
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7
Small, Dual, High-Efficiency Buck Controller for Notebooks MAX1761
Pin Description
PIN 1 2 3 NAME FB1 OUT1 REF FUNCTION Feedback Input for the 2.5V PWM. Connect FB1 to GND for a fixed 2.5V output. Connect a resistive voltage-divider to FB1 to adjust OUT1 from 1V to 5.5V. FB1 regulates to 1V (see Adjusting VOUT section) . Output Voltage Connection for PWM1. OUT1 senses the output voltage to set the regulator on-time and is connected internally to a 160k feedback input in fixed-output mode. 2V Reference Voltage Output. Bypass REF to GND with 0.1F (min) capacitor. Can supply 50A for external loads. When ON1 = High, Normal/Forced PWM Mode Selection and OUT2 On/Off Control Input ON2 CONDITION 4 ON2 LOW (ON2 < 0.5V) HIGH (2V < ON2 < VL) Floating 5 6 7 8 9 10 11 12 V+ ON1 OUT2 FB2 DH2 CS2 DL2 GND MODE SELECTED OUT1 is enabled in normal mode; OUT2 is shut down. Both outputs are enabled in normal mode. Both outputs are enabled in forced-PWM mode.
Battery Voltage. V+ is the input for the VL regulator and DH gate drivers and is also used for PWM one-shot timing. On/Off Control Input. Drive ON1 high to enable the device. Drive ON1 low to enter micropower shutdown mode. Both REF and VL are disabled in shutdown. ON1 may be pinstrapped to V+. Output Voltage Connection for PWM2. OUT2 senses the output voltage to set the regulator on-time and is connected internally to a 160k feedback input in fixed-output mode. Feedback Input for the 1.8V PWM. Connect FB2 to GND for a fixed 1.8V output. Connect a resistive voltage-divider to FB2 to adjust OUT2 from 1V to 5.5V. FB2 regulates to 1V (see Adjusting VOUT section) . High-Side Gate Driver Output for PWM2. Swings between GND and V+. Current-Sense Connection for PWM2. Connect CS2 to the drain of the low-side driver. Alternatively, connect CS2 to the junction of the source of the low-side FET and a current-sense resistor to GND. Low-Side Gate Driver Output for PWM2. DL2 swings between GND and VL. Combined Power and Analog Ground Linear Regulator Output. VL is the output of the 4.65V internal linear regulator, capable of supplying 25mA for external loads. The VL pin also serves as the supply input for the DL gate driver and the analog/logic blocks. VL can be overdriven by an external 5V supply to improve efficiency. Bypass VL to GND with a 4.7F ceramic capacitor. Low-Side Gate Driver Output for PWM1. DL1 swings between GND and VL. Current-Sense Connection for PWM1. Connect CS1 to the drain of the low-side driver. Alternatively, connect CS1 to the junction of the source of the low-side FET and a current-sense resistor to GND. High-Side Gate Driver Output for PWM1. DH1 swings between GND and V+.
13
VL
14 15 16
DL1 CS1 DH1
8
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Small, Dual, High-Efficiency Buck Controller for Notebooks MAX1761
5V < VBATT < 20V
10
10F V+ VOUT1 2.5V 220F R1 CS1 R2 LX1 7H DL1 DH1
0.1F
ON1 DH2 LX2 7H DL2 R3 CS2 R4 VOUT2 +1.8V 220F
MAX1761
OUT1 VL ON2 4.7F FB1 GND
OUT2 REF 0.1F FB2
Figure 1. Typical Application Circuit
Typical Application Circuit
The typical application circuit in Figure 1 generates two low-voltage rails for general-purpose use in notebook and subnotebook computers (I/O supply, fixed CPU core supply, DRAM supply). This DC-DC converter steps down a battery or AC adapter voltage to voltages from 1.0V to 5.5V with high efficiency and accuracy. See Table 1 for a list of components for common applications. Table 2 lists component manufacturers.
nates external boost capacitors and diodes, reducing PC board area and cost. The MAX1761 can step down input voltages from 5V to 20V, to outputs ranging from 1V to 5.5V on either output. Dual Mode feedback inputs allow fixed output voltages of 2.5V and 1.8V for OUT1 and OUT2, respectively; or, a resistive voltage-divider can be used to adjust the output voltages from 1V to 5.5V. Other appropriate applications for this device are digital cameras, large PDAs, and handy-terminals.
Detailed Description
The MAX1761 dual buck controller is designed for lowvoltage power supplies in notebook and subnotebook computers. Maxim's proprietary Quick-PWM pulsewidth modulation circuit (Figure 2) is specifically designed for handling fast load steps while maintaining a relatively constant operating frequency over a wide range of input voltages. The Quick-PWM architecture circumvents the poor load-transient timing problems of fixed-frequency current-mode PWMs while preventing problems caused by widely varying switching frequencies in conventional constant-on-time and constant-offtime PWM schemes. This MAX1761 controls two synchronously rectified outputs with complementary N- and P-channel MOSFETs. Using the P-channel for the high-side MOSFET elimi-
V+ Input and VL +5V Logic Supplies
The MAX1761 has a 5V to 20V input voltage supply range. A linear regulator powers the control logic and other internal circuitry from the input supply pin (V+). The linear regulator's 4.65V output is available at VL and can supply 25mA to external circuitry. When used as an external supply, bypass VL to GND with a 4.7F capacitor. VL is turned off when the device is in shutdown, and drops to approximately 4V when the device experiences an output voltage fault. The MAX1761 includes an input undervoltage lockout (UVLO) circuit that prevents the device from switching until VL > 4.25V (max). UVLO ensures there is sufficient drive for the external MOSFETs, prevents the high-side MOSFET from being turned on for near 100% duty cycle, and keeps the output in regulation. The UVLO
9
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Small, Dual, High-Efficiency Buck Controller for Notebooks MAX1761
Table 1. Component Selection for Standard Applications
COMPONENT Input Range Frequency Complementary P- and N-Channel MOSFETs 2.5V AT 2.0A 5V to 18V 350kHz Fairchild FDS8958A 2.5V AT 3.5A 5V to 18V 350kHz Siliconix IRF7319 1.8V AT 2.0A 5V to 18V 250kHz Fairchild FDS8958A 3.3V AT 2A 5V to 18V 350kHz Fairchild FDS8958A
Inductor
7H Sumida CDRH1047R0NC 10F, 25V Taiyo Yuden TMK432BJ106KM 330F, 10V Kemet T510X337K101 R1 = Short R2 = Open
3.5H Sumida CDRH1273R5NC 2 x 10F, 25V Taiyo Yuden TMK432BJ106KM 2 x 330F, 10V Kemet T510X337K010 R1 = 1k R2 = 1k
7H Sumida CDRH1047R0NC 10F, 25V Taiyo Yuden TMK432BJ106KM 330F, 10V Kemet T510X337K010 R3 = Short R4 = Open
10H Sumida CDRH104100NC 10F, 25V Taiyo Yuden TMK432BJ106KM 330F, 10V Kemet T510X337K010 R1 = Short R2 = Open
Input Capacitor
Output Capacitor Current-Sense Feedback Resistors
Table 2. Component Suppliers
SUPPLIER Fairchild Semiconductor Kemet Panasonic Rohm Sanyo Siliconix Sumida Taiyo Yuden PHONE 408-822-2181 408-986-0424 847-468-5624 760-929-2100 619-661-6835 408-988-8000 847-956-0666 408-573-4150 WEB www.fairchildsemi.com www.kemet.com www.panasonic. com www.rohmelectronics. com www.secc.co.jp www.vishay.com www.sumida.com www.t-yuden.com
Voltage Reference (REF)
The internal 2V reference is accurate to 1% (max) over temperature and can supply a 50A load current. Bypass REF to GND with a 0.1F capacitor when REF is unloaded. Use a 0.22F capacitor when applying an external load.
Free-Running Constant-On-Time PWM Controller with Input Feed-Forward
The Quick-PWM control architecture is a constant-ontime, current-mode type with voltage feed-forward (Figure 3). This architecture relies on the output ripple voltage to provide the PWM ramp signal. Thus, the output filter capacitor's ESR acts as a feedback resistor. The control algorithm is simple: the high-side switch ontime is determined solely by a one-shot whose period is inversely proportional to input voltage and directly proportional to output voltage (see the On-Time One-Shot section). Another one-shot sets a minimum off-time (400ns typical). The on-time one-shot is triggered if the error comparator is low, the low-side switch current is below the current-limit threshold, and the minimum offtime one-shot has timed out.
comparator has 40mV hysteresis to prevent startup oscillations on slowly rising input voltages. If VL is not driven externally, then V+ should be at least 5V to ensure proper operation. If V+ is running from a 5V (10%) supply, V+ should be externally connected to VL. Overdriving the VL regulator with an external 5V supply also increases the MAX1761's efficiency.
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Small, Dual, High-Efficiency Buck Controller for Notebooks MAX1761
VIN VL CL LINEAR REG 2V VREF VIN REF CREF
VL
REF
OUT1 CIN1
V+ ON1 DL1 DH1 Q1 DRIVER DH
MAX1761
VIN CIN2 DH2 DH DRIVER PWM CONTROL BLOCK ZERO CROSSING
VIN
DH2
Q3
ZCC1
PWM CONTROL BLOCK ZERO CROSSING
ZCC2
CS1 ILIM ILIM1 L1 OUT1 COUT1 DL1 D1 Q2 DL1 DRIVER DL DL -0.1V VL VL DL2 ILIM ILIM2
CS2
VOS -0.1V
L2 OUT2
DL2 DRIVER
Q4
D2
COUT2
OUT1
OUT SHDN GND
OUT SHDN
OUT2
ON1
ON1
ON2
ON2
Figure 2. Functional Diagram
On-Time One-Shot
The heart of the PWM core is the one-shot that sets the high-side switch on-time for both controllers. This fast, low-jitter, adjustable one-shot includes circuitry that varies the on-time in response to battery and output voltage. The high-side switch on-time is inversely proportional to the battery voltage as measured by the V+ input, and proportional to the output voltage. This algorithm results in a nearly constant switching frequency despite the absence of a fixed-frequency clock generator. The benefits of a constant switching frequency are
twofold: first, the switching noise occurs at a known frequency and is easily filtered; second, the inductor ripple current remains relatively constant, resulting in predictable output voltage ripple and a relatively simple design procedure. The difference in frequencies between OUT1 and OUT2 prevents audio-frequency "beating" and minimizes crosstalk between the two SMPS. The on-times can be calculated by using the equation below that references the K values listed in Table 3. VOUT_ + 0.1V On - Time = K VIN The 0.1V offset term accounts for the expected drop across the low-side MOSFET switch.
Table 3. On-Time One-Shot
DEVICE OUT1 OUT2 K (s) 2.857 4.000 MIN (kHz) 318 227 TYP (kHz) 350 250 MAX (kHz) 428 278
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Small, Dual, High-Efficiency Buck Controller for Notebooks MAX1761
VIN
ON-TIME COMPUTE
OUT
TOFF Q 1-SHOT TRIG Q 1-SHOT S Q S R Q R
TO DH DRIVER INPUT
TON TRIG 1-SHOT Q
TO DL DRIVER INPUT
FROM ZERO-CROSSING DETECTOR FROM CURRENT-LIMIT COMPARATOR ERROR AMP REF REF -30% GAIN DRIVER x2
MAX1761 UVP SHDN ON/OFF CONTROL UVP LATCH FEEDBACK MUX (SEE FIGURE 12) OUT FROM OUT
SHDN
TIMER
FB
FROM FEEDBACK
Figure 3. PWM Controller (One Side Only)
The maximum on-time and minimum off-time, tOFF(MIN), one-shots restrict the continuous-conduction output voltage. The worst-case dropout performance occurs with the minimum on-time and the maximum off-time, so the worst-case duty cycle for VIN = 6V, VOUT1 = 5V is given by: Duty Cycle = t ON(MIN) t ON(MIN) + t OFF(MAX) =
Resistive voltage drops in the inductor loop and the dead-time effect cause switching-frequency variations. Parasitic voltage losses decrease the effective voltage applied to the inductor. The MAX1761 compensates by shifting the duty cycle to maintain the regulated output voltage. The resulting change in frequency is: = VOUT + VDROP1 t ON (VIN + VDROP2 )
2.054s = 80.4% 2.054s + 500ns The duty cycle is ideally determined by the ratio of input-to-output voltage (Duty Cycle = V OUT /V IN ). Voltage losses in the loop cause the actual duty cycle to deviate from this relationship. See the Dropout Performance section for more information. Equate the off-time duty cycle restriction to the nonideal input/output voltage duty cycle ratio. Typical units will exhibit better performance. Operation of any power supply in dropout will greatly reduce the circuit's transient response, and some additional bulk capacitance may be required to support fast load changes.
VDROP1 is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and PC board resistances; VDROP2 is the sum of the resistances in the charging path; and tON is the on-time calculated by the MAX1761. In forced PWM mode, the dead-time effect increases the effective on-time, reducing the switching frequency as one or both dead times. This occurs only at light or negative loads when the inductor current reverses. Under these conditions, the inductor's EMF causes the switching node of the inductor to go high during the dead time, extending the effective on-time.
12
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Small, Dual, High-Efficiency Buck Controller for Notebooks
Automatic Pulse-Skipping Switchover
In normal operation, the MAX1761's PWM control algorithm automatically skips pulses at light loads. Comparators at each CS_ input in the MAX1761 truncate the low-side switch's on-time at the point where the inductor current drops to zero. This occurs when the inductor current is operating at the boundary between continuous and discontinuous conduction mode (Figure 4). This threshold is equal to 1/2 the peak-to-peak ripple current, which is inversely proportional to the inductor value: ILOAD(SKIP) K x VOUT V + - VOUT 2L V+
Forced PWM Operation (ON2 floating)
The low-noise, forced-PWM mode (ON2 floating) disables the zero-crossing current comparator that controls the low-side switch on-time. The resulting low-side gate-drive waveform is forced to become the complement of the high-side gate-drive waveform. This, in turn, causes the inductor current to reverse at light loads as the PWM loop strives to maintain a constant duty ratio of VOUT/V+. The benefit of forced-PWM mode is that it keeps the switching frequency nearly constant, but it results in a higher no-load battery current that can be 10mA to 40mA, depending on the gate capacitance of the external MOSFETs. Forced-PWM mode is most useful for reducing audiofrequency noise, improving load-transient response, and providing sink-current capability for dynamic output voltage adjustment. Multiple-output applications that use a flyback transformer or coupled inductor also benefit from forced-PWM operation because the continuous switching action improves cross-regulation.
MAX1761
where K is the on-time scale factor listed in Table 3. For example, in the typical application circuit (Figure 1), with V OUT1 = 2.5V, V+ = 15V, L = 9H, and K = 2.857s (Table 3), switchover to pulse-skipping operation occurs at ILOAD = 0.33A or about 1/8 full load. The crossover point occurs at an even lower value if a swinging (soft-saturation) inductor is used. The switching waveforms may appear noisy and asynchronous when light loading causes pulse-skipping operation; this is a normal operating condition that improves light-load efficiency. Trade-offs in PFM noise vs. light-load efficiency are made by varying the inductor value. Generally, lower inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. Penalties for using higher inductor values include larger physical size and degraded load-transient response (especially at low input-voltage levels).
Low-Side Current-Limit Sensing
The current-limit circuit employs a unique "valley" current-sensing algorithm that uses the on-state resistance of the low-side MOSFET as a current-sensing element. If the current-sense signal is above the current-limit threshold, the PWM is not allowed to initiate a new cycle (Figure 5). The actual peak current is greater than the current-limit threshold by an amount equal to the inductor ripple current. Therefore, the exact currentlimit characteristic and maximum load capability are a function of the MOSFET on-resistance, inductor value, and input voltage. The reward for this uncertainty is robust, lossless overcurrent sensing. When combined with the undervoltage protection circuit, this currentlimit method is effective in almost every circumstance. There is also a negative current limit that prevents excessive reverse inductor currents when VOUT is sinking current (forced PWM mode only). The negative current-limit threshold is set to approximately 120% of the positive current limit. Carefully observe the PC board layout guidelines to ensure that noise and DC errors do not corrupt the current-sense signals seen by CS_. Mount or place the IC close to the low-side MOSFET with short, direct traces, making a Kelvin-sense connection to the source and drain terminals. If greater current-limit accuracy is desired, CS can be connected to an external sense resistor inserted between the source of the low-side switch and ground (Figure 6). The resulting current limit will be ILIM = 0.1V / RSENSE, and it will have 8% error.
13
i V + -VOUT = t L INDUCTOR CURRENT
-IPEAK
ILOAD = IPEAK/2
0 ON-TIME
TIME
Figure 4. Pulse-Skipping/Discontinuous Crossover Point
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Small, Dual, High-Efficiency Buck Controller for Notebooks
IPEAK
ILOAD INDUCTOR CURRENT
ILIMIT
0
TIME
Figure 5. "Valley" Current-Limit Threshold Point
V+ DH VOUT DL CS
MAX1761
DH output and prevents the low-side FET from turning on until DH is fully off. The same considerations should be used for routing the DH signal to the high-side FET. Since the transition time for a P-channel switch can be much longer than an N-channel switch, the dead time prior to the high-side PMOS turning on will be more pronounced than in other synchronous step-down regulators, which use high-side N-channel switches. On the high-to-low transition, the voltage on the inductor's "switched" terminal flies below ground until the low-side switch turns on. A similar dead-time spike occurs on the opposite low-to-high transition. Depending upon the magnitude of the load current, these spikes usually have a minor impact on efficiency. The high-side drivers (DH_) swing from V+ to GND and will typically source/sink 0.6A from the gate of the Pchannel MOSFET. The low-side driver (DL_) swings from VL to ground and will typically source 0.5A and sink 0.9A from the gate of the N-channel FET. The internal pulldown transistors that drive DL low are robust, with a 2.0 (typ) on-resistance. This helps prevent DL from being pulled up when the high-side switch turns on, due to capacitive coupling from the drain to the gate of the low-side MOSFET. This places some restrictions on the FETs that can be used. Using a low-side FET with smaller gate-to-drain capacitance can prevent these problems.
MAX1761
Shutdown and Mode Control Inputs
OUT FB
Figure 6. Using a Low-Side Current-Sense Resistor
MOSFET Gate Drivers
The DH and DL outputs are optimized for driving moderate-sized power MOSFETs. The MOSFET drive capability is stronger for the low-side switch. This is consistent with the low duty factor seen in the notebook computer environment where a large V+ to VOUT differential exists. An adaptive dead-time circuit monitors the DL output and prevents the high-side FET from turning on until DL is fully off. There must be a low-resistance, low-inductance path from the DL driver to the MOSFET gate for the adaptive dead-time circuit to work properly. Otherwise, the sense circuitry in the MAX1761 will interpret the MOSFET gate as "off" while there is still charge left on the gate. Use very short, wide traces measuring 10 to 20 squares or less (50mils to 100mils wide if the MOSFET is 1 inch from the device). Similar to the DL output, an adaptive dead-time circuit also monitors the
14
The MAX1761 has two inputs (ON1, ON2) that control the operating modes of the two regulators. Asserting ON1 low places both regulators in micropower shutdown mode, in which both VL and REF are disabled. When ON1 is high, OUT1 is enabled, with VL and REF active. ON2 serves a dual function: it is a shutdown control for OUT2, and it determines the switching mode for both regulators. When ON2 is low (ON2 < 0.5V), OUT2 is disabled and OUT1 operates in normal mode. Floating ON2 places both outputs in forced PWM mode. When ON2 is high (2V < ON2 < VL), both regulators run in normal operating mode. Toggling ON1 from low to high resets the fault latch (Table 4).
Output Undervoltage Protection
The output undervoltage protection function is similar to foldback current limiting but employs a timer rather than a variable current limit. If the MAX1761 output voltage is under 70% (typ) of the nominal output voltage 20ms after coming out of shutdown, then both PWMs are latched off and will not restart until V+ is cycled or ON1 is toggled low to high.
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Small, Dual, High-Efficiency Buck Controller for Notebooks MAX1761
Table 4. Operating Mode Control Summary
MODE Shutdown ON1 Enabled Forced PWM Normal Operation ON1 ON1 < 0.5V 2.0V < ON1 < V+ 2.0V < ON1 < V+ 2.0V < ON1 < V+ X ON2 < 0.5V Floating 2.0V < ON2 VL ON2 DESCRIPTION Both OUT1 and OUT2 off, VL and REF disabled OUT1 on in normal mode, OUT2 off Both OUT1 and OUT2 on in forced PWM mode Both OUT1 and OUT2 on in normal mode
Thermal Fault Protection
The MAX1761 features a thermal fault protection circuit. When the temperature rises above +160C, the DL lowside gate-driver outputs latch high until ON1 is toggled or V+ is cycled. The fault threshold has 10C of thermal hysteresis, which prevents the regulator from restarting until the die cools off.
erally exhibit ILOAD = ILOAD(MAX) 80%. 3) Inductor Operating Point. This choice provides trade-offs between size and efficiency. Low inductor values cause large ripple currents, resulting in the smallest size, but poor efficiency and high output noise. The minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load). Inductor values lower than this grant no further sizereduction benefit. The MAX1761's pulse-skipping algorithm initiates skip mode at the critical conduction point. So, the inductor operating point also determines the load-current value at which PWM/skip mode switchover occurs. The optimum point is usually found between 20% and 50% ripple current. The inductor ripple current also impacts transientresponse performance, especially at low VIN - VOUT differentials. Low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. The amount of output sag is also a function of the maximum duty factor, which can be calculated from the ontime and minimum off-time: VSAG = (ILOAD(MAX) )2 x L 2CF x DUTY(V + (MIN) - VOUT )
POR and Soft-Start
Power-on reset (POR) occurs when V+ falls below approximately 2V, resetting the fault latch and preparing the PWM for operation once the power is cycled. VL undervoltage lockout (UVLO) circuitry inhibits switching and forces the DL gate driver low until VL rises above 4.25V, whereupon an internal digital soft-start timer begins to ramp up the maximum allowed current limit. The ramp occurs in five steps: 20%, 40%, 60%, 80%, and 100%; 100% current is available after 1.7ms.
Design Procedure
Firmly establish the input voltage range and the maximum load current before choosing the inductor operating point (ripple current ratio). The following three factors determine the SMPS design using the MAX1761: 1) Input Voltage Range. The maximum value (V+(max)) must accommodate the worst-case high AC adapter voltage. The minimum value (V+(min)) must account for the lowest battery voltage after drops due to connectors, fuses, and battery selector switches. If there is a choice at all, lower input voltages result in better efficiency. 2) Maximum Load Current. There are two values to consider, the peak load current (ILOAD(MAX)) and the continuous load current (ILOAD). The peak load current determines the instantaneous component stresses and filtering requirements and thus drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. The continuous load current determines the thermal stresses and thus drives the selection of input capacitors, MOSFETs, and other critical heat-contributing components. Modern notebook CPUs gen-
Inductor Selection
The switching frequency (on-time) and operating point (% ripple or LIR) determine the inductor value as follows: L= VOUT (V + - VOUT ) V+ x x LIR x ILOAD(MAX)
Example: ILOAD(MAX) = 2.5A, V+(max) = 20V, VOUT1 = 2.5V, f = 350kHz, 35% ripple current or LIR = 0.35:
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Small, Dual, High-Efficiency Buck Controller for Notebooks MAX1761
Output Capacitor Selection
2.5V(20V - 2.5V) L= = 7.1H 20V x 350kHz x 0.35 x 2.5A Find a low-loss inductor having the lowest possible DC resistance that fits in the allotted dimensions. Ferrite cores are often the best choice, although powdered iron is inexpensive and works well at 250kHz. The core must be large enough not to saturate at the peak inductor current (IPEAK): IPEAK = ILOAD(MAX) - 1/2 LIR ILOAD(MAX) = (1 - 0.5 LIR) ILOAD(MAX) The output filter capacitor must have low enough effective series resistance (ESR) to meet output ripple and load-transient requirements, yet have high enough ESR to satisfy the stability criterion. In CPU VCORE converters and other applications where the output is subject to violent load transients, the output capacitor's size depends on how much ESR is needed to prevent the output from dipping too low under a load transient. Ignoring the sag due to finite capacitance: RESR VDIP ILOAD(MAX)
Setting Current Limit
The minimum current-limit threshold must be great enough to support the maximum load current plus some safety margin. For the circuit in Figure 1, with a desired 2.5A maximum load current, the worst-case current limit is set at 3.0A, providing a 20% safety margin. Under these conditions, the valley of the inductor current waveform occurs at: IVALLEY = ILOAD(MAX) - 1/2 LIR ILOAD(MAX) = (1 - 0.5 LIR) ILOAD(MAX) The required valley current is IVALLEY = 3A - 1/2 (0.35) 2.5A = 2.56A. Next, the current-sense feedback voltage must be scaled taking into account the tolerance of the CS_ current-limit threshold and the maximum MOSFET drain-source on-resistance (R DS(ON) ) variation over temperature. The minimum current-limit threshold at the CS_ pins is 92mV. The worst-case maximum value for (R DS(ON) ) over temperature is 50m. At 2.56A, the voltage developed across the low-side switch is 128mV. A resistive voltage-divider with a 0.703 attenuation ratio is necessary to scale this voltage to the 92mV CS_ threshold. A current-sense resistor can be used if a more accurate current limit is needed than is available when using the MOSFET (RDS(ON) (Figure 6). Placing the sense resistor between the source of the low-side MOSFET and ground provides a very accurate sense point for the CS_ inputs. Alternatively, a small sense resistor can be used in series with the low-side MOSFET to ballast the device and reduce the temperature coefficient of the current limit when sensing at the inductor's switched node. This provides a compromise between sensing across the MOSFET device alone or using a large sense resistor.
In non-CPU applications, the output capacitor's size depends on how much ESR is needed to maintain an acceptable level of output voltage ripple: RESR Vp - p LIR x ILOAD(MAX)
The actual required F capacitance value relates to the physical size needed to achieve low ESR as well as to the chemistry of the capacitor technology. Thus, the capacitor is usually selected by ESR and voltage rating rather than by capacitance value (this is true of tantalums, SP, POS, and other electrolytics). When using low-capacitance filter capacitors, such as ceramic or polymer types, capacitor size is usually determined by the capacitance needed to prevent VSAG and VSOAR from causing problems during load transients. Generally, once enough capacitance is added to meet the VSOAR requirement, undershoot at the rising load edge is no longer a problem (see the VSAG equation in Design Procedure). The amount of overshoot due to stored inductor energy can be calculated as: V (L x IPEAK 2 ) 2CVOUT
where IPEAK is the peak inductor current.
Stability Considerations
Stability is determined by the value of the ESR zero relative to the switching frequency. The point of instability is given by the following equation: ESR =
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Small, Dual, High-Efficiency Buck Controller for Notebooks
where: ESR = 1 2 x RESR x CF CON) are preferred due to their resilience to power-up surge currents. V OUT (V + - VOUT ) IRMS = ILOAD V+
MAX1761
For a typical 350kHz application, the ESR zero frequency must be well below 100kHz, preferably below 50kHz. Tantalum and OS-CON capacitors have typical ESR zero frequencies of 15kHz. Sanyo POS capacitors have typical ESR zero frequencies of 20kHz. In the design example used for inductor selection, the ESR needed to support 50mVp-p ripple is 50mV / LIR(2.5A) = 57.1m. A single150F/6.3V Sanyo POS capacitor provides 55m (max) ESR. This ESR results in a zero at 19.3kHz, well within the bounds of stability. Don't put high-value ceramic capacitors directly across the fast feedback inputs (FB_/OUT_ to GND) without taking precautions to ensure stability. Large ceramic capacitors can have a high-ESR zero frequency and may cause erratic, unstable operation. However, it's easy to add enough series resistance by placing the capacitors a couple of inches downstream from the junction of the inductor and FB_/OUT_ pin. Unstable operation manifests itself in two related but distinctly different ways: double-pulsing and fast-feedback loop instability. Double-pulsing occurs due to noise on the output or because the ESR is so low that there isn't enough voltage ramp in the output voltage signal. This "fools" the error comparator into triggering a new cycle immediately after the 500ns minimum off-time period has expired. Double-pulsing is more annoying than harmful, resulting in nothing worse than increased output ripple. However, it can indicate the possible presence of loop instability, which is caused by insufficient ESR. Loop instability can result in oscillations at the output after line or load perturbations that can cause the output voltage to go outside the tolerance limit. The easiest method for checking stability is to apply a very fast zero-to-max load transient (refer to the MAX1761 EV kit manual) and carefully observe the output voltage ripple envelope for overshoot and ringing. It can help to simultaneously monitor the inductor current with an AC current probe. Don't allow more than one cycle of ringing after the initial step-response under- or overshoot.
Power MOSFET Selection
DC bias and output power considerations dominate the selection of the power MOSFETs used with the MAX1761. Care should be taken not to exceed the device's maximum voltage ratings. In general, both switches are exposed to the supply voltage, so select MOSFETs with VDS(MAX) greater than V+(max). Gate drive to the N-channel and P-channel MOSFETs is not symmetrical. The N-channel device is driven from ground to the logic supply VL. The P-channel device is driven from V+ to ground. The maximum rating for VGS for the N-channel device is usually not an issue. However, VGS(MAX) for the P-channel must be at least V+(max). Since V GS(MAX) is usually lower than V DS(MAX) , gate-drive constraints often dictate the required P-channel breakdown rating. For moderate input-to-output differentials, the high-side MOSFET (Q1) can be sized smaller than the low-side MOSFET (Q2) without compromising efficiency. The high-side switch operates at a very low duty cycle under these conditions, so most conduction losses occur in Q2. For maximum efficiency, choose a highside MOSFET (Q1) that has conduction losses (I2RD) equal to the switching losses (fCV+2). Make sure that the conduction losses at the minimum input voltage don't exceed the package thermal limits or violate the overall thermal budget. Similarly check for rating violations for conduction and switching losses at the maximum input voltage (see MOSFET Power Dissipation). The MAX1761 has an adaptive dead-time circuitry that prevents the high-side and low-side MOSFETs from conducting at the same time (see MOSFET Gate Drivers). Even with this protection, it is still possible for delays internal to the MOSFET to prevent one MOSFET from turning off when the other is turned on. The maximum mismatch time that can be tolerated is 60ns. Select devices that have low turn-off times, and make sure that NFET(tDOFF(MAX)) - PFET(tDON(MIN)) < 60ns, and PFET(t DOFF(MAX) ) - NFET(t DON(MIN) ) < 60ns. Failure to do so may result in efficiency-killing shootthrough currents. MOSFET selection also affects PC board layout. There are four possible combinations of MOSFETs that can be used with this switcher. The designs include: * Two dual complementary MOSFETs (Figure 7)
17
Input Capacitor Selection
The input capacitor must meet the ripple current requirement (IRMS) imposed by the switching currents. Nontantalum chemistries (ceramic, aluminum, or OS-
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Small, Dual, High-Efficiency Buck Controller for Notebooks MAX1761
* * * A dual N-channel and a dual P-channel MOSFET (Figure 8) Two single N-channels and a dual P-channel (Figure 9) Two single N-channels and two single P-channels (Figure 10) Switching losses in the high-side MOSFET can become an insidious heat problem when maximum AC adapter voltages are applied, due to the squared term in the CV2F switching-loss equation. If the high-side MOSFET you've chosen for adequate RDS(ON) at low battery voltages becomes extraordinarily hot when subjected to V+(MAX), reconsider your MOSFET choice. Calculating the power dissipation in Q1 due to switching losses is difficult since it must allow for difficult quantifying factors that influence the turn-on and turnoff times. These factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and PC board layout characteristics. The following switching-loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably including a verification using a thermocouple mounted on Q1: PD (Q1 switching) = CRSS x V +(MAX)2 x x ILOAD IGATE
There are trade-offs to each approach. Complementary devices have appropriately scaled N- and P-channel RDS(ON) and matched turn-on/turn-off characteristics. However, there are relatively few manufacturers of these specialized devices. Selection may be limited. Dual N- and P-channel MOSFETs are more widely available. As such, more efficient designs that benefit from the large low-side MOSFETs can be realized. This approach is most useful when the output power requirements for both regulators are about the same. This limitation can be sidestepped by using a dual Pchannel and two single N-channels. Using four single MOSFETs gives the greatest design flexibility but will require the most board area.
MOSFET Power Dissipation
Worst-case conduction losses occur at the duty factor extremes. For the high-side MOSFET, the worst-case power dissipation (PD) due to resistance occurs at the minimum battery voltage: V PD (Q1 resistance) = OUT x ILOAD2 x RDS(ON) V +(MIN) Generally, a small high-side MOSFET is desired to reduce switching losses at high input voltages. However, the RDS(ON) required to stay within package power-dissipation limits often limits how small the MOSFET can be. The optimum occurs when the switching (AC) losses equal the conduction (RDS(ON)) losses. High-side switching losses don't usually become an issue until the input is greater than approximately 15V.
where CRSS is the reverse transfer capacitance of Q1, and IGATE is the peak gate-drive source/sink current (1A typ). For the low-side MOSFET (Q2) the worst-case power dissipation always occurs at maximum battery voltage: VOUT 2 PD (Q2) = 1- x ILOAD x Rs V +(MAX) The absolute worst case for MOSFET power dissipation occurs under heavy overloads that are greater than ILOAD (MAX) but are not quite high enough to exceed the current limit and cause the fault latch to trip. To protect against this possibility, the circuit must be overdesigned to tolerate: ILOAD = ILIMIT (MAX) + 1/2 LIR ILOAD (MAX)
V+ D P-CHANNEL D LX1 D N-CHANNEL D S 1 D G DL1 S LX2 D N-CHANNEL S 1 G DL2 D G DH1 D P-CHANNEL S G DH2
V+
Figure 7. Dual Complementary MOSFET Design 18 ______________________________________________________________________________________
Small, Dual, High-Efficiency Buck Controller for Notebooks MAX1761
V+ 1 S P-CHANNEL DH1 G S P-CHANNEL DH2 G D LX2 D D D D D N-CHANNEL S 1 D LX1 D N-CHANNEL S G DL2 G DL1
Figure 8. Dual N- and P-Channel MOSFET Design
LX1 D D N-CHANNEL V+ 1 S P-CHANNEL DH1 G S P-CHANNEL DH2 G D D N-CHANNEL D D LX2 S S 1 S D D D G DL2 D D S 1 D S G S DL1
where I LIMIT(MAX) is the maximum valley current allowed by the current-limit circuit, including threshold tolerance and on-resistance variation. This means that the MOSFETs must be very well heatsinked. If short-circuit protection without overload protection is enough, a normal ILOAD value can be used for calculating component stresses. Choose a Schottky diode (D1, Figure 2) having a forward voltage low enough to prevent the Q2 MOSFET body diode from turning on during the dead time. As a general rule, a diode having a DC current rating equal to 1/3 of the load current is sufficient. This diode is optional and can be removed if efficiency isn't critical.
Applications Issues
Dropout Performance
The output voltage adjust range for continuous-conduction operation is restricted by the nonadjustable 500ns (max) minimum off-time one-shot. For best dropout performance, use the side with the lower switching frequency, FB2 (250kHz). When working with low input voltages, the duty-factor limit must be calculated using worst-case values for on- and off-times. Manufacturing
Figure 9. Two Single N-Channel MOSFETs and a Dual P-Channel MOSFET Design
V+ 1 S S P-CHANNEL S DH1 G D D D D
LX1 D D N-CHANNEL D D S S 1 DH2 G S DL1
V+ 1 S S P-CHANNEL S G D D D D
LX2 D D N-CHANNEL D D S S 1 G S DL2
Figure 10. Two Single N-Channel MOSFETs and Two Single P-Channel MOSFETs Design
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Small, Dual, High-Efficiency Buck Controller for Notebooks
tolerances and internal propagation delays introduce an error to the tON K-factor. Also, keep in mind that transient response performance of buck regulators operated close to dropout is poor, and bulk output capacitance must often be added (see the VSAG equation in Design Procedure). Dropout design example: VIN = 6.5V (min), VOUT = 5V, f = 350kHz, 250kHz. The required duty is (VOUT + VSW) / (V+ - VSW) = (5V + 0.1V) / (6.5V - 0.1V) = 79.7%. The worst-case on-time for f = 350kHz is (VOUT + 0.1V) / V+ K = 5.1V / 6.5V 2.857s-V 90% = 2.017s. The IC duty-factor limitation is: Duty = t ON(MAX) t ON(MAX) + t OFF(MIN) =
MAX1761
VL regulator will increase the drive on the low-side MOSFETs, thereby lowering their RDS(ON) and reducing power consumption. Note that VL should not be higher than 5.5V if connected to VL. Also note, V+ should not be brought below 5V unless VL is connected directly to V+.
PC Board Layout Guidelines
Careful PC board layout is critical to achieving low switching losses and clean, stable operation. This is especially true for dual converters, where one channel can affect the other. The switching power stages require particular attention (Figure 13). Refer to the MAX1761 EV kit data sheet for a specific layout example. If possible, mount all of the power components on the top side of the board with their ground terminals flush against one another. Follow these guidelines for good PC board layout: * Isolate the top-side power components from the sensitive analog components on the bottom side with a ground shield. Use a separate PGND plane under the OUT1 and OUT2 sides (called PGND1 and PGND2). Avoid the introduction of AC currents into the PGND1 and PGND2 ground planes. Run the power plane ground currents on the top side only, if possible. Use a star ground connection on the power plane to minimize the crosstalk between OUT1 and OUT2. Keep the high-current paths short, especially at the ground terminals. This practice is essential for stable, jitter-free operation. Connect AGND and PGND together close to the IC. Do not connect them together anywhere else. Carefully follow the grounding instructions under Step 4 of the Layout Procedure. Keep the power traces and load connections short. This practice is essential for high efficiency. Using thick copper PC boards (2oz vs. 1oz) can enhance full-load efficiency by 1% or more. Correctly routing PC board traces is a difficult task that must be approached in terms of fractions of centimeters, where a single m of excess trace resistance causes a measurable efficiency penalty. CS_ and PGND connections to the synchronous rectifiers for current limiting must be made using Kelvin sensed connections to guarantee the current-limit accuracy. With SO-8 MOSFETs, this is best done by routing power to the MOSFETs from outside, using the top copper layer, while connecting PGND and CS_ inside (underneath) the SO-8 package.
2.017s = 80.1% 2.017s + 500ns Thus, operation at 350kHz meets the required duty cycle. A similar analysis with f = 250kHz (K = 4s-V) shows that at f = 250kHz, the maximum duty cycle is 85.0%, also meeting the required duty cycle., Remember to include inductor resistance and MOSFET on-state voltage drops (VSW) when doing worst-case dropout duty-factor calculations.
* *
Fixed Output Voltages
The MAX1761's dual-mode operation allows the selection of common voltages without requiring external components (Figure 11). Connect FB1 to GND for a fixed +2.5V output at OUT1; otherwise, connect FB1 to a resistive voltage-divider for an adjustable output. Connect FB2 to GND for a +1.8V output; otherwise, connect FB2 to a resistive voltage-divider for an adjustable output.
*
Adjusting VOUT
The output voltage can be adjusted with a resistive voltage-divider if desired (Figure 12). The equation for adjusting the output voltage is: R VOUT = VFB x 1 + 1 R2 where VFB is 1.0V, and R2 is about 10k.
*
*
Low Input Voltage Operation (V+ = +5V)
The MAX1761 can be used in applications using a 5V 10% input supply by overdriving VL with the input supply voltage, V+. This not only enables operation of the MAX1761 down to V+ = 4.5V but has the added benefit of increasing overall efficiency. Overdriving the
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Small, Dual, High-Efficiency Buck Controller for Notebooks
OUT1 FIXED 2.5V TO ERROR AMP1 TO ERROR FIXED AMP2 1.8V OUT2
switching noise away from the IC, feedback dividers, and analog bypass capacitors. * Avoid coupling switching noise into control input connections (ON1, ON2, etc.). These pins should be referenced to a quiet analog ground plane.
MAX1761
Layout Procedure
FB1 0.1V FB2
1) Place the power components first, with ground terminals adjacent (Q2 source, CIN_, COUT_). If possible, make all these connections on the top layer with wide, copper-filled areas. 2) Mount the controller IC adjacent to the synchronous rectifier MOSFETs, preferably on the back side in order to keep CS_, PGND_, and the DL_ gate-drive line short and wide. The DL_ gate trace must be short and wide, measuring 10 to 20 squares (50mils to 100mils wide if the MOSFET is 1 inch from the controller IC). 3) Place the VL capacitor near the IC controller. 4) Make the DC-DC controller ground connections as follows: near the IC, create a small analog ground plane. Use this plane for the ground connection for the REF and VL bypass capacitor, and FB_ dividers. Create another small ground island for PGND, and use it for the V+ bypass capacitor, placed very close to the IC. Connect the AGND and the PGND together under the IC (this is the only connection between AGND and PGND). 5) On the board's top side (power planes), make a star ground to minimize crosstalk between the two sides. The top-side star ground is a star connection of the input capacitors, side 1 low-side MOSFET, and side 2 low-side MOSFET. Keep the resistance low between the star ground and the sources of the low-side MOSFETs for accurate current limit. Connect the top-side star ground (used for MOSFET, input, and output capacitors) to the small PGND island with a short, wide connection (preferably just a via). If multiple layers are available (highly recommended), create PGND1 and PGND2 islands on the layer just below the top-side layer (refer to the MAX1761 EV kit for an example) to act as an EMI shield. Connect each of these individually to the star ground via, which connects the top side to the PGND plane. Add one more solid ground plane under the IC to act as an additional shield, and also connect that to the star ground via. 6) Connect the output power planes directly to the output filter capacitor positive and negative terminals with multiple vias.
0.1V
MAX1761
Figure 11. Feedback MUX
V+ DH 1/2 CS MAX1761 DL GND OUT FB R2 R1 VOUT
Figure 12. Setting VOUT with a Resistive Voltage-Divider
*
When trade-offs in trace lengths must be made, it's preferable to allow the inductor charging path to be made longer than the discharge path. For example, it's better to allow some extra distance between the input capacitors and the high-side MOSFET than to allow distance between the inductor and the lowside MOSFET or between the inductor and the output filter capacitor. Ensure that the OUT connection to COUT is short and direct. However, in some cases it may be desirable to deliberately introduce some trace length between the OUT inductor node and the output filter capacitor (see Stability Considerations). Route high-speed switching nodes (CS_, DH_, and DL_) away from sensitive analog areas (REF, FB_). Use a PGND as an EMI shield to keep radiated
*
*
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21
Small, Dual, High-Efficiency Buck Controller for Notebooks MAX1761
USE AGND PLANE TO: - BYPASS VL AND REF - TERMINATE EXTERNAL FB DIVIDER (IF USED) - PIN-STRAP CONTROL INPUTS USE PGND PLANE TO: - BYPASS V+ - CONNECT PGND TO THE TOPSIDE STAR GROUND AGND
VOUT1 C3
GND C4
VOUT2
D1
D2
L1
C2
C1
L2
VIA TO PGND P1 N1 CONNECT PGND TO AGND BENEATH THE MAX1761 AT ONE POINT ONLY AS SHOWN. VL VBATT NOTE: EXAMPLE SHOWN IS FOR DUAL COMPLEMENTARY MOSFET. P2 N2
Figure 13. PC Board Layout Example
Chip Information
TRANSISTOR COUNT: 6045
22
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Small, Dual, High-Efficiency Buck Controller for Notebooks
Package Information
QSOP.EPS
MAX1761 MAX1761
Note: The MAX1761 does not have a heat slug.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 23 (c) 2000 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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